The present invention relates to a nonvolatile semiconductor memory device, more specifically to a flash EEPROM in which a memory cell is made of an MOSFET comprising both a floating gate and a control gate, and data is stored based on the amount of charges stored in the floating gate. In particular, the present invention is directed to a virtual grounded type flash EEPROM.
This application is based on Japanese Patent Application No. 9-126137, filed May 16, 1997, the content of which is incorporated herein by reference.
FIG. 1 shows the memory cell array of a conventional flash EEPROM. FIG. 2A is a plan view showing part of the memory cell array depicted in FIG. 1, and FIG. 2B is a sectional view taken along line 2B--2B in FIG. 2A. In FIG. 2B, illustration of an oxide film is omitted.
In the conventional flash EEPROM shown in FIG. 1 and FIGS. 2A and 2B, data is written in a memory cell by applying a high voltage to a word line (row line) WL and a bit line (column line) BL and applying a reference potential (e.g., a ground potential) to the common source VSS of memory cells. Since, therefore, a current is allowed to flow through the memory cell, charges are injected in the floating gate. When data is erased from the memory cell, charges are injected in the floating gates of all memory cells. After the floating gates of all memory cells are thereby set in a uniform state, all word lines are set at the reference potential level. In this state, a high voltage is applied to the common source VSS of the memory cells, and charges are thereby made to emit from the floating gates to the source by utilization of a tunnel effect, thereby erasing data from the memory cell.
In this type of EEPROM, the bit lines BL are formed of aluminum, and the drain regions of adjacent two memory cells are commonly connected to the bit line. Due to this structure, the area used for connection is inevitably wide and gives rise to a low manufacturing yield.
In consideration of the above circumstances, flash EEPROMs having a virtual grounded structure are under development. FIG. 3 shows the memory cell array of such a flash EEPROM. FIG. 4A is a plan view showing part of the memory cell array shown in FIG. 3, and FIG. 4B is a sectional view taken along line 4B--4B in FIG. 4A.
In the EEPROM having a virtual grounded structure, N.sup.+ regions, used as sources and drains of memory cells, are connected to bit lines BL1-BL9 (i.e., column lines). Since the bit lines BL1 to BL9 are formed in those N.sup.+ regions which are under control gates CG, it is not necessary to provide a connection element to connect the bit lines BL1-BL9 and the memory cells 11-88 together, unlike the memory cells shown in FIGS. 2A and 2B. Accordingly, the memory cell area can be reduced, and the connection between the bit lines and memory cells does not lower the manufacturing yield.
A description will now be given as to how data is written in a memory cell of the EEPROM of a virtual grounded structure, with charges stored in the floating gate of the memory cell. By way of example, let us consider the case where data is written in memory cell 12. In this case, a high voltage is applied to both word line WL1 (i.e., a row line) and bit line BL2, thereby setting bit line BL3 at a reference potential level (e.g., a ground potential level). In this state, a current flows through the memory cell 12, thus permitting the floating gate to store charges. Although the bit line BL1 is in the electrically floated condition at the time, the memory cell 11 is turned on due to the high voltage applied to the word line WL1. Since the high voltage is applied to the bit line BL2, the bit line BL1 is charged through the memory cell 11 in an amount corresponding to the parasitic capacitance of the bit line BL1. In order to prevent the floating gate of the memory cell 11 to store charges in spite of the charged state of the bit line BL1, an offset transistor T.sub.off is provided for each of the memory cells, as shown in FIG. 4B. The offset transistor T.sub.off has its channel portion controlled by the control gate CG. Even when data is written in the memory cell 12, the offset transistor T.sub.off connected to the bit line BL2 to which a high voltage is applied, serves to prevent the floating gate FG of the memory cell 11 from storing charges.
At the same time, however, the use of the offset transistor T.sub.off inevitably increases the memory cell size because the offset transistor T.sub.off is incorporated in the memory cell.